1. Field of the Invention
This invention relates to a D/A converter (digital/analog converter) circuit (DAC) and, more particularly, to a DAC for use in a driver circuit of a semiconductor device. Further, the invention relates to a semiconductor device using such a DAC.
2. Description of the Related Art
Recently, researches and developments have been actively made on the thin film transistors (TFTs) using, in an active layer, a polysilicon film formed on a glass substrate. The TFT using a polysilicon film has a mobility higher by two orders of magnitude as compared to the TFT using an amorphous silicon film, and hence can sufficiently acquire a current value required for operating a circuit even where a TFT gate width is down scaled. Consequently, a system-on-panel is possible to realize having a pixel region of a matrix-formed flat display panel and a driver circuit thereof formed on the same substrate.
Realizing a system-on-panel makes it possible to reduce the cost owing to the reduction of display assembling and inspection processes. It also makes feasible the reduction in flat-panel display size and enhancement of definition.
In pursuing size reduction and definition enhancement furthermore of the flat display panel, it is problematic to realize a DAC capable of operating at high speed but less in occupation area on a substrate.
The DACs, although existing in various kinds, include representatively a capacitive divider type and a resistive divider type. The capacitive divider type DAC can operate at high speed with less area as compared to the resistive divider type.
FIG. 11 shows an example of a prior-art DAC of a capacitive divider type. The prior-art capacitive divider type DAC shown in FIG. 11 has switches SW[1]-SW[n] in the number of n to be controlled by the bits of n-bit digital signals D1-Dn, capacitances C, 2C, . . . , 2nxe2x88x921C in the number of n respectively connected to the switches, and a resetting switch SWR. The prior-art DAC is connected with a power source A (voltage VA) and a power source B (voltage VB). The power sources A and B are kept at different voltages. The voltage of an analog signal outputted from the DAC is supplied onto an output line.
Note that, in the present description, voltage corresponds to a potential difference from a ground potential.
The corresponding-bit digital signals are respectively inputted to the switches SW[1]-SW[n]. Whether the capacitance is to be connected to the power source A or to the power source B is selected depending upon the information of 0 or 1 possessed by the input digital signal.
The operation of the prior-art DAC is explained in due order. The operation of the prior-art DAC is explained by separation with a reset period TR and a write period TA.
At first, in a reset period TR, the reset switch SWR closes. The digital signal is also reset to connect all the switches SW[1]-SW[n] to the same power source. It is herein assumed that connections are to the power source B. FIG. 12A shows an equivalent circuit diagram of the prior-art DAC at immediately before terminating the reset period. Note that CT means a resultant capacitance of all the capacitances.
After terminating the reset period TR, a write period TA commences to open the reset switch SWR. Subsequently, the digital signal in each bit having an arbitrary piece of information of 0 or 1 controls the switch SW[1]-SW[n]. The capacitances are connected to the power source A or B depending upon the bit of information. Due to this, the capacitances in the number of n are charged and thereafter placed in a steady state. The equivalent circuit diagram at this time is shown in FIG. 12B. Note that CA means a resultant capacitance of the capacitance connected to the power source A while CB a resultant capacitance of the capacitance connected to the power source B.
Due to a sequence of operations in the foregoing reset period TR and write period TA, the digital signal can be converted into an analog signal.
The capacitive divider type DAC is expected in proceeding the size reduction of the flat panel display because its high-speed operation with comparatively less area as compared to the resistive divider type DAC as mentioned above. However, as the digital signal is increased in bits in order to enhance the definition of the flat panel display, it becomes difficult even for the capacitive divider type DAC to suppress an occupation area on the substrate.
Should a capacitive divider type DAC be designed with a reduced capacity in order to suppress its occupation area, reduced is the area and value of a capacitance corresponding to the lowermost order bit. In the capacitance, somewhat deviation occurs in capacitance value due to mask deviation or the like during manufacture. loosening of patterning, unexpected parasitic capacitance, etc. For this reason, the design with a reduced capacitance increases the deviation ratio of the capacitance corresponding to the lowermost bit to its capacitance value. This makes it difficult to form a capacitive divider DAC favored in linearity.
Meanwhile, the resistive divider type DAC, if the corresponding signal is increased in bits, causes increase in output resistance to make difficult high-speed operation besides making impossible the reduction of area.
In view of the foregoing problem, it is a problem to manufacture a DAC capable of reducing the area and operating at high speed even where the digital signals are increased in bits, in order to further reduce the size and enhance the definition of a flat panel display.
The present inventor has provided capacitances one-to-one correspondingly to the bits of the lower order bit digital signals instead of providing capacitances one-to-one correspondingly to the bits. It has been considered that, in a reset period, a voltage having a height corresponding to the higher order bit digital signal is provided to the one electrodes (first electrodes) of the capacitances to thereby charge the capacitances while, in a write period, a voltage having a height corresponding to the lower order bit digital signals is provided to the other electrodes (second electrodes) of the capacitances to thereby charge the capacitances. Hereinafter, a reset period is referred to as a precharge period.
Specifically, the capacitances are charged in a precharge period by controlling the operation of a resistive divider DAC or selector circuit due to a higher order bit digital signals.
In the case of a DAC corresponding, for example, to n-bit digital signals D1-Dn of the invention, there are provided a resistive divider type DAC (R-DAC) or selector circuit corresponding to the higher order (nxe2x88x92m)-bit (m less than n) digital signals Dm+1-Dn and capacitances in the number of m corresponding to the lower order m bits of D1-Dm. Hereinafter, the capacitance in the number of m corresponding to the lower m bits are referred merely to as a capacitance (CU).
The values of the capacitances in the number of m are represented as CU[1]=C, CU[2]=2C, CU[3]=22C, . . . , CU[mxe2x88x921]=2mxe2x88x922C and CU[m]=2mxe2x88x921C (C is a constant), in the order of the capacitance corresponding to the lower order bit digital signal.
The DAC of the invention is connected to a power source A (voltage VA), a power source B (voltage VB), a power source C (voltage VC) and a power source D (voltage VD). In a write period TA, voltage is supplied to the first electrode of the capacitances CU in the number of m by the power source C and power source D.
Meanwhile, the resistive divider type DAC or selector circuit corresponding to the higher order nxe2x88x92m bits possessed by the DAC of the invention is connected to the power source A and power source B. In a precharge period TP, the higher order (nxe2x88x92m)-bit digital signals are converted into an analog signal. In the present description, the analog signal is referred to as a precharge analog signal (voltage VP). The voltage of a precharge analog signal outputted from the resistive divider type DAC or selector circuit is supplied to the second electrodes of the capacitances CU in the number of m to charge these capacitances.
The second electrodes of all the capacitances CU are connected to one output line. Consequently, the voltage on the output line, in other words the voltage of an analog signal to be outputted from the DAC, is determined depending on the charge stored in the write period and precharge period.
The above configuration can form a DAC corresponding to high-bit digital signals without losing linearity while making use of the merit of the capacitive divider type that driving is possible at high speed and area can be comparatively suppressed.